In order to ensure reliability of semiconductor integrated circuits, burn-in tests in which products are placed in a severe environment for operation are carried out. In the burn-in test, improvement in a so-called toggle rate and stress coverage during a finite time has become a challenge. Japanese Patent Kokai Publication No. JP-P2002-340988A, for example, introduces a pseudo dynamic burn-in method in which an instruction code (program) for the test is stored in a built-in ROM and a method in which activation by scanning is used in combination, thereby activating a functional unit (an operating unit in the publication) by a higher toggle rate.
Further, there is also well known a following method: when an electrically rewritable non-volatile memory such as a so-called flash EEPROM or an EEPROM is included in the semiconductor integrated circuit, data holding test data that is called a checker or a checker bar is held for memory cells arranged in a matrix (checkerboard) form. In the data holding test data, “0”s and “1”s are arranged in a checkered pattern. Then, stress application (e.g. reading a predetermined memory cell by activation of a word line, a bit line, and a sense amplifier) is performed, thereby generating a charge loss/charge gain through a defective location. The defective location thus can be detected efficiently.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2002-340988A